The invention pertains to a CMOS inverter chain with at least two N- or P-inverters which, in terms of signal flow, are disposed alternatingly in series, with the controlled current path lying between the poles of a source of DC voltage.
One such CMOS inverter chain comprising a single N-inverter and a single P-inverter which, in terms of signal flow, is in series with the N-inverter, is described in the German Offenlegungsschrift DE No. 24 50 882 A1, especially in connection with FIG. 7 thereof. Relative thereto, the respective signal input is the gate of the N-or P-intermediate transistor, while the gates of both the N- and the P-transistors which are connected in the known manner, in the case of the N-inverter, are fed with a clock signal and, in the case of the P-inverter, with a clock signal which is inverse in relation thereto. The purpose of this two-stage CMOS inverter chain is to make sure that the two nominal binary-signal levels will appear at the output of the P-inverter. Both the N-and the P-intermediate transistors merely represent the most simple case of a logic gate which, instead of them, can be inserted into the conventional type of CMOS inverter. Thus, in this arrangement it is possible, cf. FIG. 11, to dispose several logic CMOS gates in series, in terms of signalflow, and to operate them dynamically.